Apollo PRISM

This article has multiple issues. Please help improve it or discuss these issues on the talk page. (Learn how and when to remove these messages) This article includes a list of references, related reading, or external links, but its sources remain unclear because it lacks inline citations. Please help improve this article by introducing more precise citations. (June 2013) (Learn how and when to remove this message) This article needs additional citations for verification. Please help improve this article by adding citations to reliable sources. Unsourced material may be challenged and removed. Find sources: "Apollo PRISM" – news · newspapers · books · scholar · JSTOR (June 2013) (Learn how and when to remove this message) (Learn how and when to remove this message)

PRISM (Parallel Reduced Instruction Set Multiprocessor) was Apollo Computer's high-performance CPU used in their DN10000 series workstations. It was for some time the fastest microprocessor available, a high fraction of a Cray-1 in a workstation. Hewlett-Packard purchased Apollo in 1989, ending development of PRISM, although some of PRISM's ideas were later used in HP's own HP-PA Reduced instruction set computer (RISC) and Itanium processors.

PRISM was based on what would be known today as a VLIW-design, while most efforts of the era, 1988, were based on a more "pure" RISC approach. In early RISC designs, the core processor was simplified as much as possible in order to allow more of the chip's real-estate to be used for registers and simplifying the addition of instruction pipelines for improved performance.

The compilers used with the systems were expected to dedicate more time during compilation to making effective use of the registers and cleaning the instruction stream. By doing instruction scheduling in the compiler, this design avoided the problems and complexity of dynamic instruction scheduling (where instructions for multiple functional units must be selected carefully in order to avoid interdependencies between intermediate values) encountered in superscalar designs such as Digital Equipment Corporation's Alpha.

In some respects, the VLIW design can be thought of as "super-RISCy", as it offloads the instruction selection process to the compiler as well. In the VLIW design, the compiler examines the code and selects instructions that are known to be "safe", and then packages them into longer instruction words. For instance, for a CPU with two functional units, like the PRISM, the compiler would find pairs of safe instructions and stuff them into a single larger word. Inside the CPU, the instructions are simply split apart again, and fed into the selected units.

This design minimizes logical changes to the CPU as functional units are added, as the compiler is handling the instruction selection. However, this also ties the compiled code very tightly to the processor design; for instance, if a new generation of the CPU adds additional functional units, all programs running on it must be re-compiled so the compiler can re-arrange the instructions again, perhaps four-wide instead of two-wide. In comparison, a more traditional design like the PowerPC (PPC) has seen dramatic internal changes, yet code written for the first PPC's will still run without modification on the latest versions. The cost for this is an increasing amount of chip space that has to be dedicated to instruction scheduling.

The Apollo compilers were the first commercial compilers to use single static assignment techniques.

PRISM was a "pure" 32-bit design, including thirty-two 32-bit integer and thirty-two 64-bit floating point registers (overlaid by sixty-four 32-bit registers). PRISM could dispatch a single integer or one integer and one floating point instruction per clock cycle. The floating-point instruction could, in turn, combine a floating-point add and multiply in a single instruction. The compiler attempted to always pair (or triple) instructions up to maintain full use of the internal units, but if it failed to find a safe pair it simply fed in a single integer instruction. PRISM was one of the first designs to include a multiply with add/subtract/truncate in a single (five operand) instruction, so it was often described as a three-issue CPU.

The original PRISM design was introduced in 1988 in the one-to-four-CPU Apollo DN10000 workstations. The "DN" in the name refers to "Domain Node", Domain/OS being the Unix-like operating system used on all of Apollo's machines. Note that PRISM was a multi-chip CPU board, not a single microprocessor; this was fairly common for high-end CPUs at the time.

Approximately one thousand DN10000 systems were sold.

PRISM II, running at twice the clock speed, was delayed by problems in fabing, and then eventually cancelled after the HP purchase. Nevertheless, several features of the PRISM design were put into later generations of the HP-PA architecture, and the two main proponents of the VLIW concept, Intel and HP, later collaborated on the Itanium.

The PRISM was claimed to be the fastest CPU on the market during its short life-span.^[1] Benchmarking indicated that the speed of the DN10000's CPU was comparable to that of the MIPS M/2000-6, a 20 MHz R3000,^[2] but the DN10000 as a system had around twice the performance of the MIPS M/2000-6.^[3] In comparison with common RISC designs of the era, the PRISM was effectively two CPUs in one, making it roughly double the performance of a RISC CPU running at the same clock speed.^{[citation needed]}

Although the Intel i860 also used a VLIW (or properly LIW in both cases, as two is not "very" long), extracting performance from the i860 proved notoriously difficult, and in practice the PRISM was much faster.

Digital Equipment Corporation also engineered a RISC chip named PRISM during the same era, but that project was canceled in 1988, and never entered production.

• The Great CPU List, Section 5, Part II: Apollo PRISM - Superworkstation