90 nm process

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The 90 nm process refers to the technology used in semiconductor manufacturing to create integrated circuits with a minimum feature size of 90 nanometers. It was an advancement over the previous 130 nm process. Eventually, it was succeeded by smaller process nodes, such as the 65 nm, 45 nm, and 32 nm processes.

It was commercialized by the 2003–2005 timeframe, by semiconductor companies including Toshiba, Sony, Samsung, IBM, Intel, Fujitsu, TSMC, Elpida, AMD, Infineon, Texas Instruments and Micron Technology.

The origin of the 90 nm value is historical; it reflects a trend of 70% scaling every 2–3 years. The naming is formally determined by the International Technology Roadmap for Semiconductors (ITRS).

The 300 mm wafer size became mainstream at the 90 nm node. The previous wafer size was 200 mm diameter.

The 193 nm wavelength was introduced by many (but not all) companies for lithography of critical layers mainly during the 90 nm node. Yield issues associated with this transition (due to the use of new photoresists) were reflected in the high costs associated with this transition.

Since at least 1997, "process nodes" have been named purely on a marketing basis, and have no relation to the dimensions on the integrated circuit;[1] neither gate length, metal pitch or gate pitch on a "90nm" device is ninety nanometers.[2][3][4][5]


A 90 nm silicon MOSFET was fabricated by Iranian engineer Ghavam Shahidi (later IBM director) with D.A. Antoniadis and H.I. Smith at MIT in 1988. The device was fabricated using X-ray lithography.[6]

Toshiba, Sony and Samsung developed a 90 nm process during 2001–2002, before being introduced in 2002 for Toshiba's eDRAM and Samsung's 2 Gb NAND flash memory.[7][8] IBM demonstrated a 90 nm silicon-on-insulator (SOI) CMOS process, with development led by Shahidi, in 2002. The same year, Intel demonstrated a 90 nm strained-silicon process.[9] Fujitsu commercially introduced its 90 nm process in 2003[10] followed by TSMC in 2004.[11]

Gurtej Singh Sandhu of Micron Technology initiated the development of atomic layer deposition high-k films for DRAM memory devices. This helped drive cost-effective implementation of semiconductor memory, starting with 90 nm node DRAM.[12]

Intel's 90nm process has a transistor density of 1.45 million transistors per square milimeter (MTr/mm2).[13]

Example: Elpida 90 nm DDR2 SDRAM process[edit]

Elpida Memory's 90 nm DDR2 SDRAM process.[14]

  • Use of 300 mm wafer size
  • Use of KrF (248 nm) lithography with optical proximity correction
  • 512 Mbit
  • 1.8 V operation
  • Derivative of earlier 110 nm and 100 nm processes

Processors using 90 nm process technology[edit]

See also[edit]


  1. ^ "No More Nanometers – EEJournal". 23 July 2020.
  2. ^ Shukla, Priyank. "A Brief History of Process Node Evolution". design-reuse.com. Retrieved 9 July 2019.
  3. ^ Hruska, Joel. "14nm, 7nm, 5nm: How low can CMOS go? It depends if you ask the engineers or the economists..." ExtremeTech.
  4. ^ "Exclusive: Is Intel Really Starting To Lose Its Process Lead? 7nm Node Slated For Release in 2022". wccftech.com. 10 September 2016.
  5. ^ "Life at 10nm. (Or is it 7nm?) And 3nm - Views on Advanced Silicon Platforms". eejournal.com. 12 March 2018.
  6. ^ Shahidi, Ghavam G.; Antoniadis, D. A.; Smith, H. I. (December 1988). "Reduction of hot-electron-generated substrate current in sub-100-nm channel length Si MOSFET's". IEEE Transactions on Electron Devices. 35 (12): 2430–. Bibcode:1988ITED...35.2430S. doi:10.1109/16.8835.
  7. ^ "Toshiba and Sony Make Major Advances in Semiconductor Process Technologies". Toshiba. 3 December 2002. Retrieved 26 June 2019.
  8. ^ "Our Proud Heritage from 2000 to 2009". Samsung Semiconductor. Samsung. Retrieved 25 June 2019.
  9. ^ "IBM, Intel wrangle at 90 nm". EE Times. 13 December 2002. Retrieved 17 September 2019.
  10. ^ "65nm CMOS Process Technology" (PDF). Archived from the original (PDF) on 16 May 2020. Retrieved 20 June 2019.
  11. ^ "90nm Technology". TSMC. Retrieved 30 June 2019.
  12. ^ "IEEE Andrew S. Grove Award Recipients". IEEE Andrew S. Grove Award. Institute of Electrical and Electronics Engineers. Retrieved 4 July 2019.
  13. ^ "Intel's 10nm Cannon Lake and Core i3-8121U Deep Dive Review".
  14. ^ Elpida's presentation at Via Technology Forum 2005 and Elpida 2005 Annual Report

External links[edit]

Preceded by
130 nm
MOSFET manufacturing processes Succeeded by
65 nm