AES instruction set
From Wikipedia the free encyclopedia
An AES (Advanced Encryption Standard) instruction set is a set of instructions that are specifically designed to perform AES encryption and decryption operations efficiently. These instructions are typically found in modern processors and can greatly accelerate AES operations compared to software implementations. An AES instruction set includes instructions for key expansion, encryption, and decryption using various key sizes (128-bit, 192-bit, and 256-bit).
The instruction set is often implemented as a set of instructions that can perform a single round of AES along with a special version for the last round which has a slightly different method.
x86 architecture processors
AES-NI (or the Intel Advanced Encryption Standard New Instructions; AES-NI) was the first major implementation. AES-NI is an extension to the x86 instruction set architecture for microprocessors from Intel and AMD proposed by Intel in March 2008.
| ||Perform one round of an AES encryption flow|
| ||Perform the last round of an AES encryption flow|
| ||Perform one round of an AES decryption flow|
| ||Perform the last round of an AES decryption flow|
| ||Assist in AES round key generation[note 1]|
| ||Assist in AES decryption round key generation. Applies Inverse Mix Columns to round keys.|
- Westmere based processors, specifically:
- Sandy Bridge processors:
- Ivy Bridge processors
- All i5, i7, Xeon and i3-2115C only
- Haswell processors (all except i3-4000m, Pentium and Celeron)
- Broadwell processors (all except Pentium and Celeron)
- Silvermont/Airmont processors (all except Bay Trail-D and Bay Trail-M)
- Goldmont (and later) processors
- Skylake (and later) processors
Several AMD processors support AES instructions:
- Jaguar processors and newer
- Puma processors and newer
- "Heavy Equipment" processors
- Zen (and later) based processors
Hardware acceleration in other architectures
AES support with unprivileged processor instructions is also available in the latest SPARC processors (T3, T4, T5, M5, and forward) and in latest ARM processors. The SPARC T4 processor, introduced in 2011, has user-level instructions implementing AES rounds. These instructions are in addition to higher level encryption commands. The ARMv8-A processor architecture, announced in 2011, including the ARM Cortex-A53 and A57 (but not previous v7 processors like the Cortex A5, 7, 8, 9, 11, 15) also have user-level instructions which implement AES rounds.
Supporting x86 CPUs
The following chips, while supporting AES hardware acceleration, do not support AES-NI:
- AMD Geode LX processors
- VIA, using VIA PadLock
Programming information is available in ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile (Section A2.3 "The Armv8 Cryptographic Extension").
- ARMv8-A architecture
- ARM cryptographic extensions optionally supported on ARM Cortex-A30/50/70 cores
- Cryptographic hardware accelerators/engines
Whilst the RISC-V architecture does not include AES-specific instructions, a number of RISC-V chips include integrated AES co-processors. Examples include:
- Dual-core RISC-V 64 bits Sipeed-M1 support AES and SHA256.
- RISC-V architecture based ESP32-C (as well as Xtensa-based ESP32), support AES, SHA, RSA, RNG, HMAC, digital signature and XTS 128 for flash.
- Bouffalo Labs BL602/604 32-bit RISC-V supports various AES and SHA variants.
IBM z9 or later mainframe processors support AES as single-opcode (KM, KMC) AES ECB/CBC instructions via IBM's CryptoExpress hardware. These single-instruction AES versions are therefore easier to use than Intel NI ones, but may not be extended to implement other algorithms based on AES round functions (such as the Whirlpool and Grøstl hash functions).
- Atmel XMEGA (on-chip accelerator with parallel execution, not an instruction)
- SPARC T3 and later processors have hardware support for several cryptographic algorithms, including AES.
- Cavium Octeon MIPS All Cavium Octeon MIPS-based processors have hardware support for several cryptographic algorithms, including AES using special coprocessor 3 instructions.
In AES-NI Performance Analyzed, Patrick Schmid and Achim Roos found "impressive results from a handful of applications already optimized to take advantage of Intel's AES-NI capability". A performance analysis using the Crypto++ security library showed an increase in throughput from approximately 28.0 cycles per byte to 3.5 cycles per byte with AES/GCM versus a Pentium 4 with no acceleration.[failed verification][better source needed]
Most modern compilers can emit AES instructions.
Much security and cryptography software supports the AES instruction set, including the following notable core infrastructure:
- Apple's FileVault 2 full-disk encryption in macOS 10.10+
- NonStop SSH2, NonStop cF SSL Library and BackBox VTC Software in HPE Tandem NonStop OS L-series
- Cryptography API: Next Generation (CNG) (requires Windows 7)
- Linux's Crypto API
- Java 7 HotSpot
- Network Security Services (NSS) version 3.13 and above (used by Firefox and Google Chrome)
- Solaris Cryptographic Framework on Solaris 10 onwards
- FreeBSD's OpenCrypto API (aesni(4) driver)
- OpenSSL 1.0.1 and above
- Go programming language
A fringe use of the AES instruction set involves using it on block ciphers with a similarly-structured S-box, using affine isomorphism to convert between the two. SM4 and Camellia have been accelerated using AES-NI. The AVX-512 Galois Field New Instructions (GFNI) allows implementing these S-boxes in a more direct way.
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Newer x86-64 processors also support Galois Field New Instructions (GFNI) which allow implementing Camellia s-box more straightforward manner and yield even better performance.
- Intel Advanced Encryption Standard Instructions (AES-NI)
- AES instruction set whitepaper (2.93 MiB, PDF) from Intel