AMD 10h

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K10 / Family 10h
General information
Common manufacturer
Max. CPU clock rate1700 MHz to 3700 MHz
FSB speeds1000 MHz to 2000 MHz
Architecture and classification
Technology node65 nm to 32 nm
Instruction setAMD64 (x86-64)
Physical specifications
Products, models, variants
Core names
PredecessorK8 - Hammer
SuccessorBulldozer - Family 15h
Support status
iGPU unsupported

The AMD Family 10h, or K10, is a microprocessor microarchitecture by AMD based on the K8 microarchitecture.[1] The first third-generation Opteron products for servers were launched on September 10, 2007, with the Phenom processors for desktops following and launching on November 11, 2007 as the immediate successors to the K8 series of processors (Athlon 64, Opteron, 64-bit Sempron).


It appears that AMD has not used K-nomenclature (which originally stood for "Kryptonite" in the K5 processor[2]) from the time after the use of the codename K8 for the AMD K8 or Athlon 64 processor family, since no K-nomenclature naming convention beyond K8 has appeared in official AMD documents and press releases after the beginning of 2005.

The name "K8L" was first coined by Charlie Demerjian in 2005, at the time a writer at The Inquirer,[3] and was used by the wider IT community as a convenient shorthand[4] while according to AMD official documents, the processor family was termed "AMD Next Generation Processor Technology".[5]

The microarchitecture has also been referred to as Stars, as the codenames for desktop line of processors was named under stars or constellations (the initial Phenom models being codenamed Agena and Toliman).

In a video interview,[6] Giuseppe Amato confirmed that the codename is K10.

It was revealed, by The Inquirer itself, that the codename "K8L" referred to a low-power version of the K8 family, later named Turion 64, and that K10 was the official codename for the microarchitecture.[4]

AMD refers to it as Family 10h Processors, as it is the successor of the Family 0Fh Processors (codename K8). 10h and 0Fh refer to the main result of the CPUID x86 processor instruction. In hexadecimal numbering, 0Fh (h represents hexadecimal numbering) equals the decimal number 15, and 10h equals decimal 16. (The "K10h" form that sometimes pops up is an improper hybrid of the "K" code and Family identifier number.)

Schedule of launch and delivery[edit]


Historical information[edit]

In 2003, AMD outlined the features for upcoming generations of microprocessors after the K8 family of processors in various events and analyst meetings, including the Microprocessor Forum 2003.[7] The outlined features to be deployed by the next-generation microprocessors are as follows:

In June 2006, AMD executive vice president Henri Richard had an interview with DigiTimes commented on the upcoming processor developments:

Q: What is your broad perspective on the development of AMD processor technology over the next three to four years?

A: Well, as Dirk Meyer commented at our analysts meeting, we're not standing still. We've talked about the refresh of the current K8 architecture that will come in '07, with significant improvements in many different areas of the processor, including integer performance, floating point performance, memory bandwidth, interconnections and so on.

— AMD Executive Vice President, Henri Richard, Source: DigiTimes Interview with Henri Richard[8]

Live demonstrations[edit]

On November 30, 2006, AMD live demonstrated the native quad core chip known as "Barcelona" for the first time in public,[9] while running Windows Server 2003 64-bit Edition. AMD claims 70% scaling of performance in real world loads, and better performance than Intel Xeon 5355 processor codenamed Clovertown.[10]

On January 24, 2007, AMD Executive Vice President Randy Allen claimed that in live tests, in regard to a wide variety of workloads, "Barcelona" was able to demonstrate 40% performance advantage over the comparable Intel Xeon codenamed Clovertown dual-processor (2P) quad-core processors.[11] The expected performance of floating point per core would be approximately 1.8 times that of the K8 family, at the same clock speed.[12]

On May 10, 2007, AMD held a private event demonstrating the upcoming processors codenamed Agena FX and chipsets, with one demonstrated system being AMD Quad FX platform with one Radeon HD 2900 XT graphics card on the upcoming RD790 chipset. The system was also demonstrated real-time converting a 720p video clip into another undisclosed format while all 8 cores were maxed at 100% by other tasks.[13]

Sister microarchitecture[edit]

On the December 2006 analyst day, Executive vice president Marty Seyer announced a new mobile core codenamed Griffin launched in 2008 with inherited power optimizations technologies from the K10 microarchitecture, but based on a K8 design.

TLB bug[edit]

In November 2007 AMD stopped delivery of Barcelona processors after a bug in the translation lookaside buffer (TLB) of stepping B2 was discovered that could rarely lead to a race condition and thus a system lockup.[14] A patch in BIOS or software worked around the bug by disabling cache for page tables, but it was connected to a 5 to 20% performance penalty. Kernel patches that would almost completely avoid this penalty were published for Linux. In April 2008, the new stepping B3 was brought to the market by AMD, including a fix for the bug plus other minor enhancements.[15]


Fabrication technology[edit]

AMD has introduced the microprocessors manufactured at 65 nm feature width using Silicon-on-insulator (SOI) technology, since the release of K10 coincides with the volume ramp of this manufacturing process.[16]

Supported DRAM standards[edit]

The K8 family was known to be particularly sensitive to memory latency since its design gains performance by minimizing this through the use of an on-die memory controller (integrated into the CPU); increased latency in the external modules negates the usefulness of the feature. DDR2 RAM introduces some additional latency over DDR RAM since the DRAM is internally driven by a clock at one quarter of the external data frequency, as opposed to one half that of DDR. However, since the command clock rate in DDR2 is doubled relative to DDR and other latency-reducing features (e.g. additive latency) have been introduced, common comparisons based on CAS latency alone are not sufficient. For example, Socket AM2 processors are known to demonstrate similar performance using DDR2 SDRAM as Socket 939 processors that utilize DDR-400 SDRAM. K10 processors support DDR2 SDRAM rated up to DDR2-1066 (1066 MHz).[17]

While some desktop K10 processors are AM2+ supporting only DDR2, an AM3 K10 processor supports both DDR2 and DDR3. A few AM3 motherboards have both DDR2 and DDR3 slots (this does not mean that both types can be fitted at the same time), but for the most part they have only DDR3.

Lynx desktop processors only support DDR3, as they use the FM1 socket.

Microarchitecture characteristics[edit]

K10 architecture
K10 single core with overlay description, excluding the L2 cache array

Characteristics of the microarchitecture include the following:[18]

  • Form factors
    • Socket AM2+ with DDR2 for the 65 nm Phenom and Athlon 7000 Series
    • Socket AM3 with either DDR2 or DDR3 for Semprons and the 45 nm Phenom II and Athlon II Series. They can also be used on AM3+ motherboards with DDR3. Note that, while all K10 Phenom Processors are backwards compatible with Socket AM2+ and Socket AM2, some 45 nm Phenom II Processors are only available for Socket AM2+. Lynx processors do not use either AM2+ nor AM3.
    • Socket FM1 with DDR3 for Lynx processors.
    • Socket F with DDR2, DDR3 with Shanghai and later Opteron processors
  • Instruction set additions and extensions
    • New bit-manipulation instructions ABM: Leading Zero Count (LZCNT) and Population Count (POPCNT)
    • New SSE instructions named as SSE4a: combined mask-shift instructions (EXTRQ/INSERTQ) and scalar streaming store instructions (MOVNTSD/MOVNTSS). These instructions are not found in Intel's SSE4
    • Support for unaligned SSE load-operation instructions (which formerly required 16-byte alignment)[19]
  • Execution pipeline enhancements
    • 128-bit wide SSE units
    • Wider L1 data cache interface allowing for two 128-bit loads per cycle (as opposed to two 64-bit loads per cycle with K8)
    • Lower integer divide latency
    • 512-entry indirect branch predictor and a larger return stack (size doubled from K8) and branch target buffer
    • Side-Band Stack Optimizer, dedicated to perform increment/decrement of register stack pointer
    • Fastpathed CALL and RET-Imm instructions (formerly microcoded) as well as MOVs from SIMD registers to general purpose registers
  • Integration of new technologies onto CPU die:
    • Four processor cores (Quad-core)
    • Split power planes for CPU core and memory controller/northbridge for more effective power management, first dubbed Dynamic Independent Core Engagement or D. I. C. E. by AMD and now known as Enhanced PowerNow! (also dubbed Independent Dynamic Core Technology), allowing the cores and northbridge (integrated memory controller) to scale power consumption up or down independently.[20]
    • Shutting down portions of the circuits in core when not in load, named "CoolCore" Technology.
  • Improvements in the memory subsystem:
    • Improvements in access latency:
      • Support for re-ordering loads ahead of other loads and stores
      • More aggressive instruction prefetching, 32 bytes instruction prefetch as opposed to 16 bytes in K8
      • DRAM prefetcher for buffering reads
      • Buffered burst writeback to RAM in order to reduce contention
    • Changes in memory hierarchy:
      • Prefetch directly into L1 cache as opposed to L2 cache with K8 family
      • 32-way set associative L3 victim cache sized at least 2 MB, shared between processing cores on a single die (each with 512 K  of independent exclusive L2 cache), with a sharing-aware replacement policy.
      • Extensible L3 cache design, with 6 MB planned for 45 nm process node, with the chips codenamed Shanghai.
    • Changes in address space management:
      • Two 64-bit independent memory controllers, each with its own physical address space; this provides an opportunity to better utilize the available bandwidth in case of random memory accesses occurring in heavily multi-threaded environments. This approach is in contrast to the previous "interleaved" design, where the two 64-bit data channels were bounded to a single common address space.
      • Larger Tagged Lookaside Buffers; support for 1 GB page entries and a new 128-entry 2 MB page TLB
      • 48-bit memory addressing to allow for 256 TB memory subsystems[21]
      • Memory mirroring (alternatively mapped DIMM addressing),[22] data poisoning support and Enhanced RAS
      • AMD-V Nested Paging for improved MMU virtualization, claimed to have decreasing world switch time by 25%.
  • Improvements in system interconnect:
    • HyperTransport retry support
    • Support for HyperTransport 3.0, with HyperTransport Link unganging which creates 8 point-to-point links per socket.
  • Platform-level enhancements with additional functionality:
    • Five p-states allowing for automatic clock rate modulation
    • Increased clock gating
    • Official support for coprocessors via HTX slots and vacant CPU sockets through HyperTransport: Torrenza initiative.

Feature tables[edit]



APU features table


Phenom models[edit]

Agena (65 nm SOI, quad-core)[edit]

Toliman (65 nm SOI, tri-core)[edit]

Phenom II models[edit]

Thuban (45 nm SOI, hexa-core)[edit]

Zosma (45 nm SOI, quad-core)[edit]

Deneb (45 nm SOI, quad-core)[edit]

42 TWKR Limited Edition (45 nm SOI, quad-core)[edit]

AMD released a limited edition Deneb-based processor to extreme overclockers and partners. Fewer than 100 were manufactured.

The "42" officially represents four cores running at 2 GHz, but is also a reference to the answer to life, the universe, and everything from The Hitchhiker's Guide to the Galaxy.[25]

Propus (45 nm SOI, quad-core)[edit]

Heka (45 nm SOI, tri-core)[edit]

Callisto (45 nm SOI, dual-core)[edit]

Regor (45 nm SOI, dual-core)[edit]

Athlon X2 models[edit]

Kuma (65 nm SOI, dual-core)[edit]

Regor/Deneb (45 nm SOI, dual-core)[edit]

Athlon II Models[edit]

Zosma (45 nm SOI, quad-core)[edit]

Propus (45 nm SOI, quad-core)[edit]

Rana (45 nm SOI, tri-core)[edit]

Regor (45 nm SOI, dual-core)[edit]

Sargas (45 nm SOI, single-core)[edit]

Lynx (32 nm SOI, dual or quad-core)[edit]

Sempron models[edit]

Sargas (45 nm SOI, single-core)[edit]

Sempron X2 models[edit]

Regor (45 nm SOI, dual-core)[edit]

Lynx (32 nm SOI, dual-core)[edit]

Llano "APUs"[edit]

Lynx (32 nm SOI, dual or quad-core)[edit]

The first generation desktop APUs based on the K10 microarchitecture were released in 2011 (some models do not provide graphics capability, such as the Lynx Athlon II and Sempron X2).

  • Fabrication 32 nm on GlobalFoundries SOI process
  • Socket FM1
  • Die size: 228 mm2, with 1.178 billion transistors[30][31]
  • AMD K10 cores with no L3 cache
  • GPU: TeraScale 2
  • All A and E series models feature Redwood-class integrated graphics on die (BeaverCreek for the dual-core variants and WinterPark for the quad-core variants). Sempron and Athlon models exclude integrated graphics.[32]
  • Support for up to four DIMMs of up to DDR3-1866 memory
  • 5 GT/s UMI
  • Integrated PCIe 2.0 controller
  • Select models support Turbo Core technology for faster CPU operation when the thermal specification permits
  • Select models support Hybrid Graphics technology to assist a discrete Radeon HD 6450, 6570, or 6670 discrete graphics card. This is similar to the current Hybrid CrossFireX technology available in the AMD 700 and 800 chipset series
  • ISA extensions: MMX, Enhanced 3DNow!, SSE, SSE2, SSE3, SSE4a, ABM, NX bit, AMD64, Cool'n'Quiet, AMD-V
  • Models: Lynx desktop APUs and CPUs


Turion II (Ultra) models[edit]

"Caspian" (45nm SOI, dual-core)[edit]

Turion II models[edit]

"Caspian" (45nm SOI, dual-core)[edit]

"Champlain" (45nm SOI, dual-core)[edit]

Athlon II models[edit]

"Caspian" (45nm SOI, dual-core)[edit]

"Champlain" (45nm SOI, dual-core)[edit]

Sempron models[edit]

"Caspian" (45nm SOI, single-core)[edit]

Turion II Neo models[edit]

"Geneva" (45nm SOI, dual-core)[edit]

Athlon II Neo models[edit]

"Geneva" (45nm SOI, dual-core)[edit]

"Geneva" (45nm SOI, single-core)[edit]

V models[edit]

"Geneva" (45nm SOI, single-core)[edit]

"Champlain" (45nm SOI, single-core)[edit]

Phenom II models[edit]

"Champlain" (45nm SOI, quad-core)[edit]

"Champlain" (45nm SOI, tri-core)[edit]

"Champlain" (45nm SOI, dual-core)[edit]

Llano APUs[edit]

"Sabine" (32nm SOI, dual or quad-core)[edit]


There are two generations of K10-based processors for servers: Opteron 65 nm and 45 nm.


AMD discontinued further development of K10 based CPUs after Thuban, choosing to focus on Fusion products for mainstream desktops and laptops and Bulldozer based products for the performance market. However, within the Fusion product family, APUs such as the first generation A4, A6 and A8-series chips (Llano APUs) continued to use K10-derived CPU cores in conjunction with a Radeon graphics core. K10 and its derivatives were phased out of production by the introduction of Trinity-based APUs in 2012, which replaced the K10 cores in the APU with Bulldozer-derived cores.

Family 11h and 12h derivatives[edit]

Turion X2 Ultra Family 11h[edit]

The Family 11h microarchitecture was a mixture of both K8 and K10 designs with lower power consumption for laptop that was marketed as Turion X2 Ultra and was later replaced by completely K10-based designs.[1]

Fusion Family 12h[edit]

The Family 12h microarchitecture is a derivative of the K10 design:[37][38]

  • Both CPU and GPU were re-used to avoid complexity and risk
  • Distinct Software and Physical integration makes Fusion (APU) microarchitectures different
  • Power-saving improvements including clock gating
  • Improvements to hardware pre-fetcher
  • Redesigned memory controller
  • 1MB L2 cache per core
  • No L3 cache
  • Two new buses for on-die GPU to access memory (called Onion and Garlic interfaces)
    • AMD Fusion Compute Link (Onion) – interfaces to CPU cache and coherent system memory (see cache coherence)
    • Radeon Memory Bus (Garlic) – dedicated non-coherent interface connected directly to memory

Media discussions[edit]

Note: These media discussions are listed in ascending date of publication.

See also[edit]


  1. ^ a b "List of AMD CPU microarchitectures - LeonStudio". LeonStudio - CodeFun. 3 August 2014. Archived from the original on 26 September 2020. Retrieved 12 September 2015.
  2. ^ Hesseldahl, Arik (2000-07-06). "Why Cool Chip Code Names Die". Retrieved 2007-07-14.
  3. ^ "The Inquirer report". The Inquirer. Archived from the original on September 6, 2007.{{cite web}}: CS1 maint: unfit URL (link)
  4. ^ a b Valich, Theo. "AMD explains K8L misnomer". The Inquirer. Archived from the original on February 10, 2007. Retrieved 2007-03-16.{{cite news}}: CS1 maint: unfit URL (link)
  5. ^ Official Announcement of "AMD Next Generation Processor Technology"
  6. ^ Video interview of Giuseppe Amato (AMD's Technical Director, Sales and Marketing EMEA) Archived 2009-07-12 at in February 2007
  7. ^ Microprocessor Forum 2003 presentation slide
  8. ^ AMD's vision for next few years - an interview with Henri Richard
  9. ^ "AMD Demonstrates Its Quad Core Server Chips". 2006-11-30.
  10. ^ "AMD Demonstrates Barcelona; The First True, Native Quad Core Opteron". 2006-11-30.
  11. ^ "AMD Expects Quad Core Barcelona to Outperform Clovertown by 40%". 2007-01-25. Archived from the original on 2007-02-27. Retrieved 2007-04-19.
  12. ^ "Go to 'Barcelona' over 'Cloverton'". 2007-01-23.
  13. ^ "TGDaily report". Archived from the original on 2007-09-26. Retrieved 2007-05-11.
  14. ^ "Understanding AMD's TLB Processor Bug". Daily Tech. Archived 2009-02-18 at the Wayback Machine. December 5, 2007
  15. ^ "TLB Bug – in the Past". Xbit Labs. Archived 2009-02-09 at the Wayback Machine. March 26, 2008
  16. ^ "An AMD Update: Fab 36 Begins Shipments, Planning for 65 nm process and AM2 Performance". AnandTech. 2006-04-04.
  17. ^ "AMD's next-generation Star supports DDR2-1066 & SSE4a". HKEPC Hardware. Retrieved 2007-03-19.
  18. ^ Shimpi, Anand Lal. "Barcelona Architecture: AMD on the Counterattack". AnandTech. Archived from the original on 19 March 2007. Retrieved 2007-03-18.
  19. ^ Case, Loyd. "AMD Unveils Barcelona Quad-Core Details". Ziff Davis. Retrieved 2007-03-18.[dead link]
  20. ^ "AMD Next Generation Processor Technology Slides". HardOCP. 2006-08-22.
  21. ^ "BIOS and Kernel Developer's Guide (BKDG) For AMD Family 10h Processors" (PDF). p. 24. Archived from the original (PDF) on June 9, 2011. Retrieved 2010-05-29. Physical address space increased to 48 bits.
  22. ^ "BIOS and Kernel Developer's Guide (BKDG) for AMD Family 15h Models 10h-1Fh Processors" (PDF). Advanced Micro Devices. June 4, 2013. p. 340. Retrieved January 25, 2015.
  23. ^ In this article, the conventional prefixes for computer memory denote base-2 values whereby "kilobyte" (KB) = 210 bytes.
  24. ^ a b c d e f g h i "List of Unlockable AMD CPUs".
  25. ^ "Legit Reviews - Technology News & Reviews". 27 June 2022.
  26. ^ a b "AMD Athlon II Key Architectural Features". Advanced Micro Devices. Archived from the original on December 2, 2010. Retrieved July 8, 2010.
  27. ^ Athlon II: Viele neue Exemplare der neuen Einsteiger-Prozessoren von AMD
  28. ^ In arrivo nuovi processori Athlon II da AMD Archived July 10, 2011, at the Wayback Machine
  29. ^ "AMD Phenom II X6: Thuban the Dragon". Archived from the original on 2014-07-16. Retrieved 2018-03-29.
  30. ^ Theo Valich (28 May 2012). "AMD Comes Clean on Transistor Numbers With FX, Fusion Processors". Retrieved 23 August 2013.
  31. ^ Anand Lal Shimpi (27 September 2012). "AMD A10-5800K & A8-5600K Review: Trinity on the Desktop, Part 1". Retrieved 23 August 2013.
  32. ^ "AMD launches A-Series and the first 32nm Athlon II X4 CPUs". Retrieved 2013-11-10.
  33. ^ "The 2009 AMD Mainstream Platform". Archived from the original on 2012-05-27. Retrieved 2014-04-30.
  34. ^ a b "AMD M880G Chipset". Retrieved 2014-04-30.
  35. ^ "The 2010 AMD Mainstream Platform". Retrieved 2014-04-30.
  36. ^ "The 2010 AMD Ultrathin Platform". Archived from the original on 2012-10-31. Retrieved 2014-04-30.
  37. ^ David Kanter (27 June 2011). "AMD Fusion Architecture and Llano". Real World Tech. Retrieved 12 September 2015.
  38. ^ Pierre Boudier; Graham Sellers (June 2011). "Memory System on Fusion APUs - The Benefits of Zero Copy" (PDF). AMD Fusion Developer Summit.

External links[edit]