Sam Naffziger
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Sam Naffziger | |
|---|---|
| Born | Samuel Naffziger |
| Alma mater | California Institute of Technology (BS) Stanford University (MSc) |
| Employer | AMD |
Samuel Naffziger is an American electrical engineer who has been employed at Advanced Micro Devices in Fort Collins, Colorado since 2006. He was named a Fellow of the Institute of Electrical and Electronics Engineers (IEEE) in 2014 for his leadership in the development of power management and low-power processor technologies.[1] He is also the Senior Vice President and Product Technology Architect at AMD.[2]
Education[edit]
Naffziger received a Bachelor of Science degree in electrical engineering from the California Institute of Technology and a Master of Science in computer engineering from Stanford University.[3]
Career[edit]
Early career[edit]
For eight years, Naffziger led the Itanium design team at Hewlett-Packard before moving to Intel in 2002.[4] At Intel, Naffziger played a leading role in the introduction of two major Itanium models at the International Solid State Circuits Conference, the McKinley processor in 2002 and Montecito in 2005.[5]
2006-present: Advanced Micro Devices[edit]
Naffziger was an architect lead on AMD's Ryzen processors that launched in March 2017.[6] He was the lead advocate for AMD's Ryzen and Epyc lines to move to a modular, chiplet-based approach.[7] Towards the end of 2017, Naffziger began to lead the AMD graphics team in bringing a chiplet architecture to graphics with the RDNA 3 architecture, released in 2022.[8]
Academic works[edit]
- Wang, Alice; Naffziger, Samuel, eds. (2010). Adaptive Techniques for Dynamic Processor Optimization: Theory and Practice (PDF). Cham: Springer. ISBN 978-0-387-76471-9.
- Singh, Teja; Schaefer, Alex; Rangarajan, Sundar; John, Deepesh; Henrion, Carson; Schreiber, Russell; Rodriguez, Miguel; Kosonocky, Stephen; Naffziger, Samuel; Novak, Amy (2018). "Zen: An Energy-Efficient High-Performance x86 Core". IEEE Journal of Solid-State Circuits. 53 (1): 102–114.
- Naffziger, Samuel; Beck, Noah; Burd, Thomas; Lepak, Kevin; Loh, Gabriel H.; Subramony, Mahesh; White, Sean (2021). Pioneering Chiplet Technology and Design for the AMD EPYC™ and Ryzen™ Processor Families: Industrial Product. 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA). Valencia, Spain. pp. 57–70.
- Papermaster, Mark; Kosonocky, Stephen; Loh, Gabriel H.; Naffziger, Samuel (2021). A New Era of Tailored Computing. 2021 Symposium on VLSI Circuits. Kyoto, Japan. pp. 1–2.
- Wuu, John; Agarwal, Rahul; Ciraula, Michael; Dietz, Carl; Johnson, Brett; Johnson, Dave; Schreiber, Russell; Swaminathan, Raja; Walker, Will; Naffziger, Samuel (2022). 3D V-Cache: the Implementation of a Hybrid-Bonded 64MB Stacked Cache for a 7nm x86-64 CPU. 2022 IEEE International Solid- State Circuits Conference (ISSCC). San Francisco, CA. pp. 428–429.
References[edit]
- ^ "2014 elevated fellow". IEEE Fellows Directory. Archived from the original on December 31, 2014. Retrieved April 12, 2017.
- ^ "Sam Naffziger". AMD. Retrieved April 3, 2023.
- ^ "AMD Senior VP and Low-Power Guru, Samuel Naffziger, Addresses the Looming Electronics Power Challenge". All About Circuits. Retrieved April 3, 2023.
- ^ Kanellos, Michael (January 25, 2002). "Intel's Itanium: Plan B in the works". ZDNet. Retrieved April 3, 2023.
- ^ Shankland, Stephen (March 29, 2006). "AMD lures high-ranking Itanium designer". ZDNet. Retrieved April 3, 2023.
- ^ Chuang, Tamara (March 3, 2017). "AMD unveils faster, half-price computer chip". The Denver Post. Retrieved April 3, 2023.
- ^ Alcorn, Paul; Walton, Jarred (June 23, 2022). "Into the GPU Chiplet Era: An Interview With AMD's Sam Naffziger". Tom's Hardware. Retrieved April 3, 2023.
- ^ Brosdahl, Peter (November 22, 2022). "AMD Lead Engineer Sam Naffziger Explains Advantages of RDNA3 Chiplet Design". The FPS Review. Retrieved April 3, 2023.
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