# Adder (electronics)

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Components - Adder–subtractor (±)Subtractor (−)Divider (÷)Bitwise opsSee also
- Kochanski multiplication (exponentiation)
- Multiply–accumulate operation
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An **adder**, or **summer**,^{[1]} is a digital circuit that performs addition of numbers. In many computers and other kinds of processors, adders are used in the arithmetic logic units (ALUs). They are also used in other parts of the processor, where they are used to calculate addresses, table indices, increment and decrement operators and similar operations.

Although adders can be constructed for many number representations, such as binary-coded decimal or excess-3, the most common adders operate on binary numbers. In cases where two's complement or ones' complement is being used to represent negative numbers, it is trivial to modify an adder into an adder–subtractor. Other signed number representations require more logic around the basic adder.

## History[edit]

In 1937, Claude Shannon demonstrated binary addition in his graduate thesis at MIT.^{[2]}

## Binary adders[edit]

### Half adder[edit]

The **half adder** adds two single binary digits and . It has two outputs, sum () and carry (). The carry signal represents an overflow into the next digit of a multi-digit addition. The value of the sum is . The simplest half-adder design, pictured on the right, incorporates an XOR gate for and an AND gate for . The Boolean logic for the sum (in this case ) will be whereas for the carry () will be . With the addition of an OR gate to combine their carry outputs, two half adders can be combined to make a full adder.^{[3]} The half adder adds two input bits and generates a carry and sum, which are the two outputs of a half adder. The input variables of a half adder are called the augend and addend bits. The output variables are the sum and carry.

The truth table for the half adder is:

**Inputs****Outputs****A****B****C**_{out}**S**0 0 0 0 0 1 0 1 1 0 0 1 1 1 1 0

Various half adder digital logic circuits:

- Half adder in action.
- Schematic of half adder implemented with five NAND gates.
- Schematic symbol for a 1-bit half adder.

### Full adder[edit]

A **full adder** adds binary numbers and accounts for values carried in as well as out. A one-bit full-adder adds three one-bit numbers, often written as , , and ; and are the operands, and is a bit carried in from the previous less-significant stage.^{[4]} The full adder is usually a component in a cascade of adders, which add 8, 16, 32, etc. bit binary numbers. The circuit produces a two-bit output. Output carry and sum are typically represented by the signals and , where the sum equals .

A full adder can be implemented in many different ways such as with a custom transistor-level circuit or composed of other gates. The most common implementation is with:

The above expressions for and can be derived from using a Karnaugh map to simplify the truth table.

In this implementation, the final OR gate before the carry-out output may be replaced by an XOR gate without altering the resulting logic. This is because when A and B are both 1, the term is always 0, and hence can only be 0. Thus, the inputs to the final OR gate can never be both 1's (this is the only combination for which the OR and XOR outputs differ).

Due to the functional completeness property of the NAND and NOR gates, a full adder can also be implemented using nine NAND gates,^{[5]} or nine NOR gates.

Using only two types of gates is convenient if the circuit is being implemented using simple integrated circuit chips which contain only one gate type per chip.

A full adder can also be constructed from two half adders by connecting and to the input of one half adder, then taking its sum-output as one of the inputs to the second half adder and as its other input, and finally the carry outputs from the two half-adders are connected to an OR gate. The sum-output from the second half adder is the final sum output () of the full adder and the output from the OR gate is the final carry output (). The critical path of a full adder runs through both XOR gates and ends at the sum bit . Assumed that an XOR gate takes 1 delays to complete, the delay imposed by the critical path of a full adder is equal to:

The critical path of a carry runs through one XOR gate in adder and through 2 gates (AND and OR) in carry-block and therefore, if AND or OR gates take 1 delay to complete, has a delay of:

The truth table for the full adder is:

**Inputs****Outputs****A****B****C**_{in}**C**_{out}**S**0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1

Inverting all inputs of a full adder also inverts all of its outputs, which can be used in the design of fast ripple-carry adders, because there is no need to invert the carry.^{[6]}

Various full adder digital logic circuits:

- Full adder in action.
- Schematic of full adder implemented with nine NAND gates.
- Schematic of full adder implemented with nine NOR gates.
- Full adder with inverted outputs with single-transistor carry propagation delay in CMOS
^{[6]} - Schematic symbol for a 1-bit full adder with
*C*_{in}and*C*_{out}drawn on sides of block to emphasize their use in a multi-bit adder

### Adders supporting multiple bits[edit]

#### Ripple-carry adder[edit]

It is possible to create a logical circuit using multiple full adders to add *N*-bit numbers. Each full adder inputs a , which is the of the previous adder. This kind of adder is called a **ripple-carry adder** (RCA), since each carry bit "ripples" to the next full adder. Note that the first (and only the first) full adder may be replaced by a half adder (under the assumption that ).

The layout of a ripple-carry adder is simple, which allows fast design time; however, the ripple-carry adder is relatively slow, since each full adder must wait for the carry bit to be calculated from the previous full adder. The gate delay can easily be calculated by inspection of the full adder circuit. Each full adder requires three levels of logic. In a 32-bit ripple-carry adder, there are 32 full adders, so the critical path (worst case) delay is 3 (from input to carry in first adder) + 31 × 2 (for carry propagation in latter adders) = 65 gate delays.^{[7]} The general equation for the worst-case delay for a *n*-bit carry-ripple adder, accounting for both the sum and carry bits, is:

A design with alternating carry polarities and optimized AND-OR-Invert gates can be about twice as fast.^{[8]}^{[6]}

#### Carry-lookahead adder[edit]

To reduce the computation time, engineers devised faster ways to add two binary numbers by using carry-lookahead adders (CLA). They work by creating two signals ( and ) for each bit position, based on whether a carry is propagated through from a less significant bit position (at least one input is a 1), generated in that bit position (both inputs are 1), or killed in that bit position (both inputs are 0). In most cases, is simply the sum output of a half adder and is the carry output of the same adder. After and are generated, the carries for every bit position are created. Some advanced carry-lookahead architectures are the Manchester carry chain, Brent–Kung adder (BKA),^{[9]} and the Kogge–Stone adder (KSA).^{[10]}^{[11]}

Some other multi-bit adder architectures break the adder into blocks. It is possible to vary the length of these blocks based on the propagation delay of the circuits to optimize computation time. These block based adders include the carry-skip (or carry-bypass) adder which will determine and values for each block rather than each bit, and the carry-select adder which pre-generates the sum and carry values for either possible carry input (0 or 1) to the block, using multiplexers to select the appropriate result *when* the carry bit is known.

By combining multiple carry-lookahead adders, even larger adders can be created. This can be used at multiple levels to make even larger adders. For example, the following adder is a 64-bit adder that uses four 16-bit CLAs with two levels of lookahead carry units.

Other adder designs include the carry-select adder, conditional sum adder, carry-skip adder, and carry-complete adder.

#### Carry-save adders[edit]

If an adding circuit is to compute the sum of three or more numbers, it can be advantageous to not propagate the carry result. Instead, three-input adders are used, generating two results: a sum and a carry. The sum and the carry may be fed into two inputs of the subsequent 3-number adder without having to wait for propagation of a carry signal. After all stages of addition, however, a conventional adder (such as the ripple-carry or the lookahead) must be used to combine the final sum and carry results.

### 3:2 compressors[edit]

A full adder can be viewed as a *3:2 lossy compressor*: it sums three one-bit inputs and returns the result as a single two-bit number; that is, it maps 8 input values to 4 output values. Thus, for example, a binary input of 101 results in an output of 1 + 0 + 1 = 10 (decimal number 2). The carry-out represents bit one of the result, while the sum represents bit zero. Likewise, a half adder can be used as a *2:2 lossy compressor*, compressing four possible inputs into three possible outputs.

Such compressors can be used to speed up the summation of three or more addends. If the number of addends is exactly three, the layout is known as the carry-save adder. If the number of addends is four or more, more than one layer of compressors is necessary, and there are various possible designs for the circuit: the most common are Dadda and Wallace trees. This kind of circuit is most notably used in multiplier circuits, which is why these circuits are also known as Dadda and Wallace multipliers.

## Quantum adders[edit]

Using only the Toffoli and CNOT quantum logic gates, it is possible to produce quantum full- and half-adders.^{[12]}^{[13]}^{[14]} The same circuits can also be implemented in classical reversible computation, as both CNOT and Toffoli are also classical logic gates.

Since the quantum Fourier transform have a low circuit complexity, it can efficiently be used for adding numbers as well.^{[15]}^{[16]}

## Analog adders[edit]

Just as in Binary adders, combining two input currents effectively adds those currents together. Within the constraints of the hardware, non-binary signals (i.e. with a base higher than 2) can be added together to calculate a sum. Also known as a "summing amplifier",^{[17]} this technique can be used to reduce the number of transistors in an addition circuit.

## See also[edit]

- Binary multiplier
- Subtractor
- Electronic mixer — for adding analog signals

## References[edit]

**^**Singh, Ajay Kumar (2010).*Digital VLSI Design*. Prentice Hall India. p. 321. ISBN 9788120341876 – via Google Books.**^**"Computer Circuits :: CC 210 Textbook".*textbooks.cs.ksu.edu*.**^**Lancaster, Geoffrey A. (2004).*Excel HSC Software Design and Development*. Pascal Press. p. 180. ISBN 978-1-74125175-3.**^**Mano, M. Morris (1979).*Digital Logic and Computer Design*. Prentice-Hall. pp. 119–123. ISBN 978-0-13-214510-7.**^**Teja, Ravi (2021-04-15),*Half Adder and Full Adder Circuits*, retrieved 2021-07-27- ^
^{a}^{b}^{c}Fischer, P. "Einfache Schaltungsblöcke" (PDF). Universität Heidelberg. Archived from the original (PDF) on 2021-09-05. Retrieved 2021-09-05. **^**Satpathy, Pinaki (2016).*Design and Implementation of Carry Select Adder Using T-Spice*. Anchor Academic Publishing. p. 22. ISBN 978-3-96067058-2.**^**Burgess, Neil (2011).*Fast Ripple-Carry Adders in Standard-Cell CMOS VLSI*. 20th IEEE Symposium on Computer Arithmetic. pp. 103–111.**^**Brent, Richard Peirce; Kung, Hsiang Te (March 1982). "A Regular Layout for Parallel Adders".*IEEE Transactions on Computers*.**C-31**(3): 260–264. doi:10.1109/TC.1982.1675982. ISSN 0018-9340. S2CID 17348212. Archived from the original on September 24, 2017.**^**Kogge, Peter Michael; Stone, Harold S. (August 1973). "A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations".*IEEE Transactions on Computers*.**C-22**(8): 786–793. doi:10.1109/TC.1973.5009159. S2CID 206619926.**^**Reynders, Nele; Dehaene, Wim (2015).*Ultra-Low-Voltage Design of Energy-Efficient Digital Circuits*. Analog Circuits and Signal Processing (1 ed.). Cham, Switzerland: Springer International Publishing AG Switzerland. doi:10.1007/978-3-319-16136-5. ISBN 978-3-319-16135-8. ISSN 1872-082X. LCCN 2015935431.**^**Feynman, Richard P. (1986). "Quantum mechanical computers".*Foundations of Physics*.**16**(6). Springer Science and Business Media LLC: 507–531. Bibcode:1986FoPh...16..507F. doi:10.1007/bf01886518. ISSN 0015-9018. S2CID 122076550.**^**"Code example: Quantum full adder". QuTech (Delft University of Technology (TU Delft) and the Netherlands Organisation for Applied Scientific Research (TNO)).**^**Dibyendu Chatterjee, Arijit Roy (2015). "A transmon-based quantum half-adder scheme".*Progress of Theoretical and Experimental Physics*.**2015**(9): 093A02. Bibcode:2015PTEP.2015i3A02C. doi:10.1093/ptep/ptv122.**^**Draper, Thomas G. (7 Aug 2000). "Addition on a Quantum Computer". arXiv:quant-ph/0008033.**^**Ruiz-Perez, Lidia; Juan Carlos, Garcia-Escartin (2 May 2017). "Quantum arithmetic with the quantum Fourier transform".*Quantum Information Processing*.**16**(6): 152. arXiv:1411.5949v2. Bibcode:2017QuIP...16..152R. doi:10.1007/s11128-017-1603-1. S2CID 10948948.**^**"Summing Amplifier is an Op-amp Voltage Adder". 22 August 2013.

## Further reading[edit]

- Liu, Tso-Kai; Hohulin, Keith R.; Shiau, Lih-Er; Muroga, Saburo (January 1974). "Optimal One-Bit Full-Adders with Different Types of Gates".
*IEEE Transactions on Computers*.**C-23**(1). Bell Laboratories: IEEE: 63–70. doi:10.1109/T-C.1974.223778. ISSN 0018-9340. S2CID 7746693. - Lai, Hung Chi; Muroga, Saburo (September 1979). "Minimum Binary Parallel Adders with NOR (NAND) Gates".
*IEEE Transactions on Computers*.**C-28**(9). IEEE: 648–659. doi:10.1109/TC.1979.1675433. S2CID 23026844. - Mead, Carver; Conway, Lynn (1980) [December 1979].
*Introduction to VLSI Systems*(1 ed.). Reading, MA, USA: Addison-Wesley. Bibcode:1980aw...book.....M. ISBN 978-0-20104358-7. Retrieved 2018-05-12. - Davio, Marc; Dechamps, Jean-Pierre; Thayse, André (1983).
*Digital Systems, with algorithm implementation*(1 ed.). Philips Research Laboratory, Brussels, Belgium: John Wiley & Sons, a Wiley-Interscience Publication. ISBN 978-0-471-10413-1. LCCN 82-2710. - Gosling, John (January 1971). "Review of High-Speed Addition Techniques".
*Proc. IEE*.**188**(1): 29–35. doi:10.1049/piee.1971.0004.

## External links[edit]

- Media related to Adders (digital circuits) at Wikimedia Commons
- Hardware algorithms for arithmetic modules, includes description of several adder layouts with figures.
- 8-bit Full Adder and Subtractor, a demonstration of an interactive Full Adder built in JavaScript solely for learning purposes.
- Interactive Full Adder Simulation (requires Java), Interactive Full Adder circuit constructed with Teahlab's online circuit simulator.
- Interactive Half Adder Simulation (requires Java), Half Adder circuit built with Teahlab's circuit simulator.
- 4-bit Full Adder Simulation built in Verilog, and the accompanying Ripple Carry Full Adder Video Tutorial
- Shirriff, Ken (November 2020). "Reverse-engineering the carry-lookahead circuit in the Intel 8008 processor".