Manycore processor

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Manycore processors are special kinds of multi-core processors designed for a high degree of parallel processing, containing numerous simpler, independent processor cores (from a few tens of cores to thousands or more). Manycore processors are used extensively in embedded computers and high-performance computing.

Contrast with multicore architecture[edit]

Manycore processors are distinct from multi-core processors in being optimized from the outset for a higher degree of explicit parallelism, and for higher throughput (or lower power consumption) at the expense of latency and lower single-thread performance.

The broader category of multi-core processors, by contrast, are usually designed to efficiently run both parallel and serial code, and therefore place more emphasis on high single-thread performance (e.g. devoting more silicon to out-of-order execution, deeper pipelines, more superscalar execution units, and larger, more general caches), and shared memory. These techniques devote runtime resources toward figuring out implicit parallelism in a single thread. They are used in systems where they have evolved continuously (with backward compatibility) from single core processors. They usually have a 'few' cores (e.g. 2, 4, 8) and may be complemented by a manycore accelerator (such as a GPU) in a heterogeneous system.


Cache coherency is an issue limiting the scaling of multicore processors. Manycore processors may bypass this with methods such as message passing,[1] scratchpad memory, DMA,[2] partitioned global address space,[3] or read-only/non-coherent caches. A manycore processor using a network on a chip and local memories gives software the opportunity to explicitly optimise the spatial layout of tasks (e.g. as seen in tooling developed for TrueNorth).[4]

Manycore processors may have more in common (conceptually) with technologies originating in high-performance computing such as clusters and vector processors.[5]

GPUs may be considered a form of manycore processor having multiple shader processing units, and only being suitable for highly parallel code (high throughput, but extremely poor single thread performance).

Suitable programming models[edit]

Classes of manycore systems[edit]

Specific manycore architectures[edit]

Specific manycore computers with 1M+ CPU cores[edit]

A number of computers built from multicore processors have one million or more individual CPU cores. Examples include:

Specific computers with 5 million or more CPU cores[edit]

Quite a few supercomputers have over 5 million CPU cores. When there are also coprocessors, e.g. GPUs used with, then those cores are not listed in the core-count, then quite a few more computers would hit those targets.

See also[edit]


  1. ^ Mattson, Tim (January 2010). "The Future of Many Core Computing: A tale of two processors" (PDF).
  2. ^ Hendry, Gilbert; Kretschmann, Mark. "IBM Cell Processor" (PDF).
  3. ^ Olofsson, Andreas; Nordström, Tomas; Ul-Abdin, Zain (2014). "Kickstarting High-performance Energy-efficient Manycore Architectures with Epiphany". arXiv:1412.5538 [cs.AR].
  4. ^ Amir, Arnon (June 11, 2015). "IBM SyNAPSE Deep Dive Part 3". IBM Research. Archived from the original on 2021-12-21.
  5. ^ "cell architecture"."The Cell architecture is like nothing we have ever seen in commodity microprocessors, it is closer in design to multiprocessor vector supercomputers"
  6. ^ Rick Merritt (June 20, 2011), "OEMs show systems with Intel MIC chips",, EE Times
  7. ^ Barker, J; Bowden, J (2013). "Manycore Parallelism through OpenMP". OpenMP in the Era of Low Power Devices and Accelerators. IWOMP. Lecture Notes in Computer Science, vol 8122. Springer. doi:10.1007/978-3-642-40698-0_4.
  8. ^ Morgan, Timothy Prickett (2021-02-10). "A First Peek At China's Sunway Exascale Supercomputer". The Next Platform. Retrieved 2021-11-18.
  9. ^ Hemsoth, Nicole (2021-04-19). "China's Exascale Prototype Supercomputer Tests AI Workloads". The Next Platform. Retrieved 2021-11-18.
  10. ^ Chen, Yu-Hsin; Krishna, Tushar; Emer, Joel; Sze, Vivienne (2016). "Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks". IEEE International Solid-State Circuits Conference, ISSCC 2016, Digest of Technical Papers. pp. 262–263.

External links[edit]