10 nm process

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In semiconductor fabrication, the International Technology Roadmap for Semiconductors (ITRS) defines the "10 nanometer process" as the MOSFET technology node following the "14 nm" node.

Since at least 1997, "process nodes" have been named purely on a marketing basis, and have no relation to the dimensions on the integrated circuit;[1] neither gate length, metal pitch or gate pitch on a "10nm" device is ten nanometers.[2][3][4] For example, GlobalFoundries' "7 nm" processes are dimensionally similar to Intel's "10 nm" process.[5] TSMC and Samsung's "10 nm" processes are somewhere between Intel's "14 nm" and "10 nm" processes in transistor density. The transistor density (number of transistors per square millimetre) is more important than transistor size, since smaller transistors no longer necessarily mean improved performance, or an increase in the number of transistors.

All production "10 nm" processes are based on FinFET (fin field-effect transistor) technology, a type of multi-gate MOSFET technology that is a non-planar evolution of planar silicon CMOS technology. Samsung first started their production of "10 nm-class" chips in 2013 for their multi-level cell (MLC) flash memory chips, followed by their SoCs using their 10 nm process in 2016. TSMC began commercial production of "10 nm" chips in 2016, and Intel later began production of "10 nm" chips in 2018.[needs update]


The ITRS's original naming of this technology node was "11 nm". According to the 2007 edition of the roadmap, by the year 2022, the half-pitch (i.e., half the distance between identical features in an array) for a DRAM was projected to be 11 nm.

In 2008, Pat Gelsinger, at the time serving as Intel's Chief Technology Officer, said that Intel saw a 'clear way' towards the "10 nm" node.[6][7]

In 2011, Samsung announced plans to introduce the "10 nm" process the following year.[8][needs update] In 2012, Samsung announced eMMC flash memory chips that are produced using the "10 nm" process.[9]

As of 2018, "10 nm" as it was generally understood was only in high-volume production at Samsung. GlobalFoundries had skipped "10 nm",[needs update] Intel had not yet started high-volume "10 nm" production, due to yield issues,[needs update] and TSMC had considered "10 nm" to be a short-lived node,[10] mainly dedicated to processors for Apple during 2017–2018, moving on to "7 nm" in 2018.[needs update]

There is also a distinction to be made between "10 nm" as marketed by foundries and "10 nm" as marketed by DRAM companies.

Technology production history[edit]

In April 2013, Samsung announced that it had begun mass production of multi-level cell (MLC) flash memory chips using a "10 nm-class" process, which, according to Tom's Hardware, Samsung defined as "a process technology node somewhere between 10-nm and 20-nm".[11] On 17 October 2016, Samsung Electronics announced mass production of SoC chips at "10 nm".[12] The technology's main announced challenge at that time had been triple patterning for its metal layer.[13][14][needs update]

TSMC began commercial production of "10 nm" chips in early 2016, before moving onto mass production in early 2017.[15]

On 21 April 2017, Samsung started shipping their Galaxy S8 smartphone, which used the company's version of the "10 nm" processor.[16][needs update] On 12 June 2017, Apple delivered second-generation iPad Pro tablets powered with TSMC-produced Apple A10X chips using the "10 nm" FinFET process.[17]

On 12 September 2017, Apple announced the Apple A11, a 64-bit ARM-based system on a chip, manufactured by TSMC using a "10 nm" FinFET process, containing 4.3 billion transistors on a die of 87.66 mm2.

In April 2018, Intel announced a delay in volume production of "10 nm" mainstream CPUs until sometime in 2019.[18] In July, the exact time was further pinned down to the holiday season.[19] In the meantime, however, they did release a low-power "10 nm" mobile chip, albeit exclusive to Chinese markets and with much of the chip disabled.[20][needs update]

In June 2018 at VLSI 2018, Samsung announced their "11LPP" and "8LPP" processes. "11LPP" was a hybrid based on Samsung "14 nm" and "10 nm" technology. "11LPP" was based on their "10 nm" BEOL, not their "20 nm" BEOL like the "14LPP". "8LPP" was based on the "10LPP" process.[21][22][needs update]

Nvidia released their GeForce 30 series GPUs in September 2020. They were at that time made on a custom version of Samsung's "8 nm" process, called "Samsung 8N", with a transistor density of 44.56 million transistors per mm2.[23][24][needs update]

Process nodes[edit]


ITRS Logic Device
Ground Rules (2015)
Samsung TSMC Intel
Process name 16/14 nm 11/10 nm 10LPE
(10 nm)
(10 nm)
(8 nm)
(8 nm)
(8 nm)
(10 nm)
10nm[25] 10nm SF
(10 nm)[a]
Transistor density (MTr / mm2) Un­known Un­known 51.82[22] 61.18[22] ? 52.51[27] 100.76[28][b]
Transistor gate pitch (nm) 70 48 68 64 ? 66 54
Interconnect pitch (nm) 56 36 51 ? ? 44 36
Transistor fin pitch (nm) 42 36 42 42 ? 36 34
Transistor fin height (nm) 42 42 49 ? ? 42 53
Production year 2015 2017 2017 production[22] 2017 production[22] 2018 production 2019 production 2021 production 2016 risk production[15]
2017 production[15]
2018 production
(Cannon Lake)[30]
2020 production
(Tiger Lake)[31]
  1. ^ For 10nm ESF renamed Intel 7, see 7 nm[26][disputed ]
  2. ^ Intel uses this formula:[29]

Transistor gate pitch is also referred to as CPP (contacted poly pitch) and interconnect pitch is also referred to as MMP (minimum metal pitch). Samsung reported their "10 nm" process as having a 64 nm transistor gate pitch and 48 nm interconnect pitch. TSMC reported their "10 nm" process as having a 64 nm transistor gate pitch and 42 nm interconnect pitch. Further investigation by Tech Insights revealed even these values to also be false, and they have been updated accordingly. In addition, the transistor fin height of Samsung's "10 nm" process was updated by MSSCORPS CO at SEMICON Taiwan 2017.[32][33][34][35][36] GlobalFoundries decided not to develop a "10 nm" node, because it believed it would be short lived.[37] Samsung's "8 nm" process was at that time the company's last to exclusively use DUV lithography.[38][needs update]

DRAM "10 nm class"[edit]

For the DRAM industry, the term "10 nm-class" is often used and this dimension generally refers to the half-pitch of the active area.[citation needed] The "10 nm" foundry structures are generally much larger.[citation needed]

Generally "10 nm class" refers to DRAM with a 10-19 nm feature size, and was first introduced c. 2016. As of 2020, there were three generations of "10 nm class" DRAM : 1x nm (19-17 nm, Gen1); 1y nm (16-14 nm, Gen2); and 1z nm (13-11 nm, Gen3).[39] 3rd Generation "1z" DRAM was first introduced c. 2019 by Samsung, and was initially stated to be produced using ArF lithography without the use of EUV lithography;[40][41] subsequent production did utilise EUV lithography.[42]

Beyond 1z Samsung named its next node (fourth generation "10 nm class") DRAM : "D1a" (expected at that time to have been produced in 2021), and beyond that "D1b" (expected at that time to have been produced in 2022)[needs update]; whilst Micron referred[needs update] to succeeding "nodes" as "D1α" and "D1β".[43] Micron announced volume shipment of 1α class DRAM in early 2021.[44]


  1. ^ "No More Nanometers – EEJournal". 23 July 2020.
  2. ^ Shukla, Priyank. "A Brief History of Process Node Evolution". design-reuse.com. Retrieved 9 July 2019.
  3. ^ Hruska, Joel. "14nm, 7nm, 5nm: How low can CMOS go? It depends if you ask the engineers or the economists..." ExtremeTech.
  4. ^ "Exclusive: Is Intel Really Starting To Lose Its Process Lead? 7nm Node Slated For Release in 2022". wccftech.com. 10 September 2016.
  5. ^ "Life at 10nm. (Or is it 7nm?) And 3nm - Views on Advanced Silicon Platforms". eejournal.com. 12 March 2018.
  6. ^ Damon Poeter (July 2008). "Intel's Gelsinger Sees Clear Path To 10nm Chips". Archived from the original on 25 April 2009. Retrieved 20 June 2009.
  7. ^ "MIT: Optical lithography good to 12 nanometers". Archived from the original on 25 September 2012. Retrieved 20 June 2009.
  8. ^ "World's Largest Fabrication Facility, Line-16". Samsung. 26 September 2011. Retrieved 21 June 2019.
  9. ^ "Samsung's new 10nm-process 64GB mobile flash memory chips are smaller, faster, better". Engadget. 15 November 2012. Retrieved 21 June 2019.
  10. ^ "10nm rollout". Archived from the original on 4 August 2018. Retrieved 4 August 2018.
  11. ^ "Samsung Mass Producing 128Gb 3-bit MLC NAND Flash". Tom's Hardware. 11 April 2013. Archived from the original on 21 June 2019. Retrieved 21 June 2019.
  12. ^ Samsung Starts Industry's First Mass Production of System-on-Chip with 10-Nanometer FinFET Technology, October 2016
  13. ^ "Samsung Starts Industry's First Mass Production of System-on-Chip with 10-Nanometer FinFET Technology". news.samsung.com.
  14. ^ "triple patterning for 10nm metal" (PDF).
  15. ^ a b c "10nm Technology". TSMC. Retrieved 30 June 2019.
  16. ^ "Buy".
  17. ^ techinsights.com. "10nm Rollout Marching Right Along". techinsights.com. Archived from the original on 3 August 2017. Retrieved 30 June 2017.
  18. ^ "Intel Corp. Delays 10nm Chip Production - Mass production is now scheduled for 2019". 29 April 2018. Retrieved 1 August 2018.
  19. ^ "Intel says not to expect mainstream 10nm chips until 2H19". 28 July 2018. Retrieved 1 August 2018.
  20. ^ "Intel's First 10nm Processor Lands In China". 15 May 2018. Retrieved 11 September 2018.
  21. ^ "VLSI 2018: Samsung's 11nm nodelet, 11LPP". WikiChip Fuse. 30 June 2018. Retrieved 31 May 2019.
  22. ^ a b c d e "VLSI 2018: Samsung's 8nm 8LPP, a 10nm extension". WikiChip Fuse. 1 July 2018. Retrieved 31 May 2019.
  23. ^ James, Dave (September 2020). "Nvidia confirms Samsung 8nm process for RTX 3090, RTX 3080, and RTX 3070 | PC Gamer". www.pcgamer.com.
  24. ^ "NVIDIA GeForce RTX 30 Ampere GPU Deep-Dive, Full Specs, Thermals, Power & Performance Detailed". 4 September 2020.
  25. ^ Demerjian, Charlie (2 August 2018). "Intel guts 10nm to get it out the door". SemiAccurate. Retrieved 29 September 2018.
  26. ^ "Intel's Process Roadmap to 2025: With 4nm, 3nm, 20A and 18A?!".
  27. ^ Schor, David (16 April 2019). "TSMC Announces 6-Nanometer Process". WikiChip Fuse. Retrieved 31 May 2019.
  28. ^ "Intel 10nm density is 2.7X improved over its 14nm node". HEXUS. Retrieved 14 November 2018.
  29. ^ Bohr, Mark (28 March 2017). "Let's Clear Up the Node Naming Mess". Intel Newsroom. Retrieved 6 December 2018.
  30. ^ Cutress, Ian (26 July 2021). "Intel's Process Roadmap to 2025: with 4nm, 3nm, 20A and 18A?!". AnandTech. Retrieved 27 July 2021.
  31. ^ "What Products Use Intel 10nm? SuperFin and 10++ Demystified".
  32. ^ "Intel Details Cannonlake's Advanced 10nm FinFET Node, Claims Full Generation Lead Over Rivals". 28 March 2017. Archived from the original on 30 March 2017. Retrieved 30 March 2017.
  33. ^ "International Technology Roadmap for Semiconductors 2.0 2015 Edition Executive Report" (PDF). Retrieved 27 December 2018.
  34. ^ Jones, Scotten (25 February 2024). "14nm 16nm 10nm and 7nm - What we know now".
  35. ^ "Qualcomm Snapdragon 835 First to 10 nm". Samsung 10LPE process
  36. ^ "10 nm lithography process". wikichip.
  37. ^ Jones, Scotten (25 February 2024). "Exclusive - GLOBALFOUNDRIES discloses 7nm process detail".
  38. ^ Shilov, Anton. "Samsung's 8LPP Process Technology Qualified, Ready for Production". www.anandtech.com.
  39. ^ Mellor, Chris (13 April 2020), "Why DRAM is stuck in a 10nm trap", blocksandfiles.com
  40. ^ Shilov, Anton (21 March 2019), "Samsung Develops Smaller DDR4 Dies Using 3rd Gen 10nm-Class Process Tech", www.anandtech.com
  41. ^ Samsung Develops Industry's First 3rd-generation 10nm-Class DRAM for Premium Memory Applications (press release), Samsung, 25 March 2019
  42. ^ Samsung Announces Industry's First EUV DRAM with Shipment of First Million Modules (press release), Samsung, 25 March 2020
  43. ^ Choe, Jeongdong (18 February 2021), "Teardown: Samsung's D1z DRAM with EUV Lithography", www.eetimes.com
  44. ^ Micron Delivers Industry's First 1α DRAM Technology (press release), Micron, 26 January 2021
Preceded by
14 nm
MOSFET manufacturing processes Succeeded by
7 nm