List of Intel CPU microarchitectures

From Wikipedia the free encyclopedia

The following is a partial list of Intel CPU microarchitectures. The list is incomplete, additional details can be found in Intel's Tick–tock model, Process–architecture–optimization model and Template:Intel processor roadmap.

x86 microarchitectures[edit]

x86 microarchitectures
Year Micro-architecture Pipeline stages Max
Process node
1978 8086 (8086, 8088) 02 05 3000 nm
1982 186 (80186, 80188) 02 025
1982 286 (80286) 03 025 1500 nm
1985 386 (80386) 06[1] 033
1989 486 (80486) 05 0100 1000 nm
1993 P5 (Pentium) 05 0200 800, 600, 350 nm
1995 P6 (Pentium Pro, Pentium II) 14 (17 with load & store/retire) 0450 500, 350, 250 nm
1997 P5 (Pentium MMX) 06 0233 350 nm
1999 P6 (Pentium III) 12 (15 with load & store/retire) 1400 250, 180, 130 nm
2000 NetBurst (Pentium 4)
20 unified with branch prediction 2000 180 nm
2002 NetBurst (Pentium 4)
(Northwood, Gallatin)
3466 130 nm
2003 Pentium M (Banias, Dothan)
Enhanced Pentium M (Yonah)
10 (12 with fetch/retire) 2333 130, 90, 65 nm
2004 NetBurst (Pentium 4, Pentium D)
31 unified with branch prediction 3800 90, 65 nm
2006 Intel Core 12 (14 with fetch/retire) 3000 65 nm
2007 Penryn (die shrink) 3333 45 nm
2008 Nehalem 20 unified (14 without miss prediction) 3600
Bonnell 16 (20 with prediction miss) 2100
2010 Westmere (die shrink) 20 unified (14 without miss prediction) 3866 32 nm
2011 Saltwell (die shrink) 16 (20 with prediction miss) 2130
Sandy Bridge 14 (16 with fetch/retire) 4000
2012 Ivy Bridge (die shrink) 4100 22 nm
2013 Silvermont 14–17 (16–19 with fetch/retire) 2670
Haswell 14 (16 with fetch/retire) 4400
2014 Broadwell (die shrink) 3700 14 nm
2015 Airmont (die shrink) 14–17 (16–19 with fetch/retire) 2640
Skylake 14 (16 with fetch/retire) 5200
2016 Goldmont 20 unified with branch prediction 2600
2017 Goldmont Plus 20 unified with branch prediction (?) 2800
2018 Palm Cove 14 (16 with fetch/retire) 3200 10 nm
2019 Sunny Cove 14–20 (misprediction) 4100
2020 Tremont 20 unified 3300
Willow Cove 14 unified 5300
2021 Cypress Cove 14 unified 5300 14 nm
Golden Cove 12 unified 5500 Intel 7
Gracemont 20 unified with misprediction penalty 4300
2022 Raptor Cove 12 unified 6000
2023 Redwood Cove Intel 4
Note: Atom/Power efficient microarchitectures are in Italic


first x86 processor; initially a temporary substitute for the iAPX 432 to compete with Motorola, Zilog, and National Semiconductor and to top the successful Z80. 8088 version, with an 8-bit bus, used in the original IBM Personal Computer.
included a DMA controller, interrupt controller, timers, and chip select logic. A small number of additional instructions. The 80188 was a version with an 8-bit bus.
first x86 processor with protected mode including segmentation based virtual memory management. Performance improved by a factor of 3 to 4 over 8086. Included instructions relating to protected mode. The 80286 had a 24-bit address bus.

32-bit (IA-32)[edit]

first 32-bit x86 processor. Introduced paging on top of segmentation which is the most commonly used memory protection technology in modern operating systems ever since. Many additional powerful and valuable new instructions.
Intel's second generation of 32-bit x86 processors, introduced built-in floating point unit (FPU), 8 KB on-chip L1 cache, and pipelining. Faster per MHz than the 386. Small number of new instructions.
original Pentium microprocessors, first x86 processor with super-scalar architecture and branch prediction.
used in Pentium Pro, Pentium II, Pentium II Xeon, Pentium III, and Pentium III Xeon microprocessors. First x86 processor to support SIMD instruction with XMM register implemented, RISC μop decode scheme, integrated register renaming and out-of-order execution. Some important new instructions, including conditional moves, which allow the avoidance of costly branch instructions. Added 36-bit physical memory addressing, "Physical Address Extension (PAE)".
commonly referred to as P7 although its internal name was P68 (P7 was used for Itanium). Used in Pentium 4, Pentium D, and some Xeon microprocessors. Very long pipeline. The Prescott was a major architectural revision. Later revisions were the first to feature Intel's x86-64 architecture, enhanced branch prediction and trace cache, and eventually support was added for the NX (No eXecute) bit to implement executable-space protection.

64-bit (x86-64)[edit]

reengineered P6-based microarchitecture used in Intel Core 2 and Xeon microprocessors, built on a 65 nm process, supporting x86-64 level SSE instruction and macro-op fusion and enhanced micro-op fusion with a wider front end and decoder, larger out-of-order core and renamed register, support loop stream detector and large shadow register file.
  • Penryn: 45 nm shrink of the Core microarchitecture with larger cache, higher FSB and clock speeds, SSE4.1 instructions, support for XOP and F/SAVE and F/STORE instructions, enhanced register alias table and larger integer register file.
released November 17, 2008, built on a 45 nm process and used in the Core i7, Core i5, Core i3 microprocessors. Incorporates the memory controller into the CPU die. Added important powerful new instructions, SSE4.2.
  • Westmere: 32 nm shrink of the Nehalem microarchitecture with several new features.
Sandy Bridge
32 nm microarchitecture, released January 9, 2011. Formerly called Gesher but renamed in 2007.[2] First x86 to introduce 256 bit AVX instruction set and implementation of YMM registers.
  • Ivy Bridge: successor to Sandy Bridge, using 22 nm process, released in April 2012.
22 nm microarchitecture, released June 3, 2013. Added a number of new instructions, including AVX2 and FMA.
  • Broadwell: 14 nm derivative of the Haswell microarchitecture, released in September 2014. Three-cycle FMUL latency, 64 entry scheduler. Formerly called Rockwell.
14 nm microarchitecture, released August 5, 2015.
  • Kaby Lake: successor to Skylake, released in August 2016, broke Intel's Tick-Tock schedule due to delays with the 10 nm process.
    • Amber Lake: ultra low power, mobile-only successor to Kaby Lake, using 14+ nm process, released in August 2018 (no architecture changes)[3]
    • Whiskey Lake: mobile-only successor to Kaby Lake Refresh, using 14++ nm process, released in August 2018 (has hardware mitigations for some vulnerabilities)[3]
  • Skylake-X: high-end desktop, workstation and server microarchitecture, released on June 19, 2017 (HEDT), July 11, 2017 (SP) and August 29, 2017 (W). Introduces support for AVX-512 instruction set.
  • Coffee Lake: successor to Kaby Lake, using 14++ nm process, released in October 2017
  • Cascade Lake: server and high-end desktop successor to Kaby Lake-X and Skylake-X, using 14++ nm process, released in April 2019
  • Comet Lake: successor to Coffee Lake, using 14++ nm process, released in August 2019[4]
  • Cooper Lake: server-only, optimized for AI oriented workloads using bfloat16, with limited availability only to Intel priority partners, using 14++ nm process, released in 2020[5][6]
Palm Cove
After releasing the Palm Cove core, Intel has changed their microarchitecture naming scheme, decoupling the CPU cores from their manufacturing nodes.[7][8]
Successor to Skylake (canceled), includes the AVX-512 instruction set.[9][10]
  • Cannon Lake: mobile-only successor of Kaby Lake, using Intel's 10 nm process, first and only microarchitecture to implement the Palm Cove core, released in May 2018. Formerly called Skymont, discontinued in December 2019.[11]
Sunny Cove
Successor to the Palm Cove core, first non-Atom core to include hardware acceleration for SHA hashing algorithms.[12]
  • Ice Lake: low power, mobile-only successor to Whiskey Lake, using 10 nm process, released in September 2019
  • Lakefield: mobile-only, Intel's first hybrid processor, released in June 2020. Sunny Cove is used in the singular performance core (P-core) of Lakefield processors.[13] AVX and more advanced instruction sets are disabled due to the E-core not supporting them.
  • Ice Lake-SP: server-only successor to Cascade Lake, using 10 nm process, released in April 2021[5][14]
Cypress Cove
Backport of Sunny Cove to Intel's 14 nm process
Willow Cove
Successor to the Sunny Cove core, includes new security features and redesigns the cache subsystem.[18]
  • Tiger Lake: successor to Ice Lake, using Intel's 10 nm SuperFin (10SF) process, released in Q4 2020
Golden Cove
Successor to the Willow Cove core, includes improvements to performance and power efficiency. Also includes new instructions.[19]
  • Alder Lake: hybrid processor, succeeds Rocket Lake and Tiger Lake; uses Intel 7 process (previously known as 10ESF),[20] released on November 4, 2021.[21] Golden Cove is used in P-cores of Alder Lake processors.[22]
  • Sapphire Rapids: server and workstation-only, successor to Ice Lake-SP, manufactured on Intel 7 process,[20][23] released on January 10, 2023. Introduces AMX.
Raptor Cove
A refresh of Golden Cove with increased L2 and L3 caches and core clocks.
  • Raptor Lake: successor to Alder Lake with increased cache sizes, core clocks and the number of E-cores, released on October 20, 2022. Manufactured using Intel 7 process. Raptor Cove is used in the P-cores while the E-cores are still implemented using Gracemont microarchitecture.

x86 ULV (Atom)[edit]

45 nm, low-power, in-order microarchitecture for use in Atom processors.
  • Saltwell: 32 nm shrink of the Bonnell microarchitecture.
22 nm, out-of-order microarchitecture for use in Atom processors, released on May 6, 2013.
  • Airmont: 14 nm shrink of the Silvermont microarchitecture.
14 nm Atom microarchitecture iteration after Silvermont but borrows heavily from Skylake processors (e.g., GPU), released in April 2016.[24][25]
  • Goldmont Plus: successor to Goldmont microarchitecture, still based on the 14 nm process, released on December 11, 2017.
10 nm Atom microarchitecture iteration after Goldmont Plus.[26]
  • Lakefield: mobile-only, Intel's first hybrid processor, released in June 2020. Tremont is used in efficiency cores (E-cores) of Lakefield processors.[13]
  • Jasper Lake: Celeron and Pentium Silver desktop and mobile processors, released in Q1 2021.
  • Elkhart Lake: embedded processors targeted at IoT, released in Q1 2021.
Intel 7 process[20] Atom microarchitecture iteration after Tremont. First Atom class core with AVX and AVX2 support.
  • Alder Lake: hybrid processor, succeeds Rocket Lake and Tiger Lake, released on November 4, 2021. Gracemont is used in E-cores of Alder Lake processors.[22]
  • Raptor Lake: a refresh of Alder Lake, released on October 20, 2022.

Other microarchitectures[edit]

IA-64 (Itanium)[edit]

original Itanium microarchitecture. Used only in the first Itanium microprocessors.
enhanced microarchitecture used in the first two generations of the Itanium 2 microprocessor. Madison is the 130 nm version.
enhanced McKinley microarchitecture used in the Itanium 2 9000- and 9100-series of processors. Added dual core, coarse multithreading, and other improvements. The Montvale update added demand-based switching (SpeedStep) and core-level lockstep execution.
enhanced microarchitecture used in the Itanium 9300 series of processors. Added quad core, an integrated memory controller, QuickPath Interconnect, and other improvements e.g. a more active SoEMT.
Itanium processor featuring an all-new microarchitecture.[27] 8 cores, decoupling in pipeline and in multithreading. 12-wide issue with partial out-of-order execution.[28]
the last Itanium. It has the same microarchitecture as Poulson, but slightly higher clock speed for the top two models.


a microarchitecture implementing the ARM architecture instruction set.
Larrabee (cancelled 2010)
multi-core in-order x86-64 updated version of P5 microarchitecture, with wide SIMD vector units and texture sampling hardware for use in graphics. Cores derived from this microarchitecture are called MIC (Many Integrated Core).


Pentium 4 / Core lines[edit]

Pentium 4 / Core roadmap
Desktop Mobile Enthusiast
180 nm P6,
Willamette 2000-11-20 Willamette Foster Foster MP
130 nm Northwood/
Mobile Pentium 4
2002-01-07 Northwood Northwood Mobile
Northwood-XE Prestonia
90 nm Prescott
2004-02-01 Prescott
Prescott 2M-XE
65 nm Cedar Mill
(Yonah only)
2006-01-05 Cedar Mill
Yonah Presler-XE Dempsey
Core Merom[29] Core 2 2006-07-27
Conroe Merom Kentsfield Woodcrest
45 nm Penryn 2007-11-11
Wolfdale Penryn Yorkfield Harpertown Dunnington
Nehalem Nehalem Previous[33]
(Core i)
Lynnfield Clarksfield Bloomfield Gainestown Beckton
32 nm Westmere 2010-01-04
Clarkdale Arrandale Gulftown Westmere-EP Westmere-EX
2 (Core i) 2011-01-09
Sandy Bridge Sandy Bridge-M Sandy Bridge-E Sandy Bridge-EP [38]
22 nm Ivy
3 2012-04-29 Ivy Bridge Ivy Bridge-M Ivy Bridge-E
Ivy Bridge-EP
Ivy Bridge-EX
Haswell Haswell 4 2013-06-02 Haswell-DT
Haswell-E Haswell-EP Haswell-EX
2014-06 Haswell-DT
14 nm Broadwell 5 2014-09-05 Broadwell-DT Broadwell-H
Broadwell-E Broadwell-EP[42] Broadwell-EX[42]
Skylake[a] Skylake 6 1 2015-08-05
Skylake-S Skylake-H
(formerly Skylake-EP/-EX)[45]
7 / 8 2016-10 Kaby Lake-S Kaby Lake-G
Kaby Lake-H
Kaby Lake-U
Kaby Lake-Y
Kaby Lake-X
8 / 9 2017-10
Coffee Lake-S Coffee Lake-B
Coffee Lake-H
Coffee Lake-U
Coffee Lake-W
8 2018-08-28 Whiskey Lake-U
8 / 10 Amber Lake-Y
2 2019-04-02 Cascade Lake-X
Cascade Lake-W
Cascade Lake-AP
Cascade Lake-SP
10 2019-09[b] Comet Lake-S Comet Lake-H
Comet Lake-U[47]
Comet Lake-Y[47]
Comet Lake-W
3 2020-06 [48][49] Cooper Lake-SP
11 2021-03 Rocket Lake-S Rocket
10 nm Palm
8 2018-05[b] Cannon Lake-U
10 3 2019-09 (mobile)[b]
2021-04 (server)
Ice Lake-U[53]
Ice Lake-Y[53]
Ice Lake-W Ice Lake-SP[54]
11 2020-09 Tiger Lake-H
Tiger Lake-H35
Tiger Lake-UP3
Tiger Lake-UP4
Intel 7[c] Golden

12 2021-11-04[17][55] Alder Lake-S Alder Lake-H
Alder Lake-P
Alder Lake-U
4 2023-01-10 Sapphire Rapids-WS Sapphire Rapids-SP
13 / 14 2022-10-20 Raptor Lake-S Raptor Lake-HX
Raptor Lake-H
Raptor Lake-P
Raptor Lake-U
5 2023-12-14 Un­known Emerald Rapids–SP
Intel 4[20] Redwood
Core Ultra
Series 1
2023-12-14[56] Meteor Lake-H
Meteor Lake-U
Intel 3 TBA Granite
6 2024 TBA Granite Rapids–SP
Intel 20A Arrow
Core Ultra 2024 TBA
Intel 18A or 20A Lunar
2024 TBA
Intel 18A Panther
2025 TBA
  1. ^ Cascade Lake and Cooper Lake microprocessors have additional instructions that enable Intel Deep Learning Boost.
  2. ^ a b c retail availability
  3. ^ Previously known as 10nm Enhanced Super Fin or 10ESF.[20]

Atom lines[58][edit]

Atom roadmap
MID, smartphone Tablet Netbook Nettop Embedded Server Communication CE
45 nm Bonnell 2008 Silverthorne Diamondville Tunnel Creek,
Un­known Sodaville
2010 Lincroft Pineview Groveland
32 nm Saltwell 2011 Medfield (Penwell & Lexington),
Clover Trail+ (Cloverview)
Clover Trail (Cloverview) Cedar Trail (Cedarview) Un­known Centerton & Briarwood Un­known Berryville
22 nm Silvermont 2013 Merrifield (Tangier),[59] Slayton,
Moorefield (Anniedale)[60]
Bay Trail-T
Bay Trail-M
Bay Trail-D
Bay Trail-I
Avoton Rangeley Un­known
014 nm[58] Airmont 2014 Binghamton & Riverton Cherry Trail-T (Cherryview)[61] Braswell[62] Denverton Cancelled Un­known Un­known
2016 Broxton Cancelled Willow Trail Cancelled
Apollo Lake
Apollo Lake[64] Denverton[65] Un­known Un­known
2017 Un­known Un­known Gemini Lake[67]
Gemini Lake Refresh[68]
Un­known Un­known Un­known
10 nm Tremont[26] 2020 Un­known Lakefield (hybrid) Lakefield (hybrid)[69]
Elkhart Lake[70]
Jasper Lake [71]
Parker Ridge[72]
Snow Ridge[73]
Un­known Un­known
Intel 7 Gracemont[74] 2021 Un­known Un­known Alder Lake (hybrid)[75]
Raptor Lake (hybrid)
Alder Lake-N [76][77]
Un­known Un­known Un­known
Intel 4 Crestmont 2023 Un­known Un­known Meteor Lake (hybrid) Grand Ridge Un­known Un­known
Intel 3 Crestmont 2024 Un­known Un­known Un­known Un­known Un­known Sierra Forest-AP Un­known Un­known
Intel 20A Skymont 2024 Un­known Un­known Arrow Lake (hybrid) Un­known Un­known Un­known
Intel 18A Darkmont 2025 Un­known Un­known Un­known Un­known Un­known Clearwater Forest-AP Un­known Un­known

See also[edit]


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External links[edit]